1. Field of the Invention
The present invention generally relates to programmable read only memories (PROMs), and more particularly, to so-called flash memories which are a form of electrically erasable programmable read only memories (EEPROMs) of high integration density.
2. Description of the Prior Art
Digital circuits and data processing systems in particular may use several different types of storage devices for various purposes and to derive various advantages from the respective characteristics thereof. For example, certain types of registers which provide output signals in a sequence which is fixed relative to the input sequence (e.g. first in-first out (FIFO) buffers) may avoid the need to store additional information regarding the identity of the data or how it may be later accessed while it is stored. Other types of memory structures allow data to be retrieved based on an address. Exemplary of the latter types of devices are random access memories and read only memories.
As is known, the former type of memory allows data stored therein to be changed at will at the expense of certain complexities of structure, such as providing for periodic refresh of dynamic RAMs or increased device counts in static RAMs. However, many of those complexities can be avoided in the latter type of memory where stored data is fixed or is only very infrequently changed. Many types of Read only memory are non-volatile and may be used to store commands or data regarding device operation during periods when the device may be disconnected from a power source.
When the application requires that data be changed from time to time, so-called programmable read only memories are often employed. Such memories often require special provisions such as irradiation with ultraviolet light or special purpose circuits to achieve rewriting of memory contents (the latter being referred to as electrically erasable read only memories (EEPROMs)) and often imposing low speed of response when cells must be individually erased and rewritten. To speed this process, so-called flash memories have been developed in which sections of memory are erased in a single operation and writing speed is enhanced.
EEPROMS in general and flash memories in particular operate by formation of a transistor with a so-called floating gate which is separated from a source of charge by a very thin oxide layer, generally referred to as a tunnelling oxide layer or simply tunnelling oxide. A control gate is formed over the floating gate but separated therefrom by a thicker oxide having a thickness similar to the gate oxide of a normal field effect transistor (FET). By applying a voltage to the control gate when charge has been placed below the floating gate by application of a suitable voltage, transfer of electrons through the tunnelling oxide for storage in the floating gate can be achieved. The charge stored in the floating gate can thereafter be detected by the conductance of the channel under the floating gate until the charge is removed by erasure.
One mechanism used in the rewriting of flash memories is channel hot electron (CHE) injection which generally requires an external high voltage power supply. However, a NAND type flash memory using Fowler-Nordheim tunneling has been proposed using only a 5 volt power supply for all operations. The Fowler-Nordheim tunnelling mechanism avoids avalanche breakdown and greatly reduces the chance of hot hole injection into the tunnelling oxide which tends to reduce the amount of stored charge representing data. As a result of the reduction of hot hole injection, a ten-fold increase in data retention time relative to the CHE injection mechanism is achieved.
As in all other types of integrated circuits at the present time, there is much interest in increasing integration density so that more circuits and/or memory cells may be placed on a single chip. Unfortunately, processes currently used for production of all types of EEPROMS and especially flash memories using Fowler-Nordheim tunnelling mechanisms are not amenable to scaling in order to increase packing density. The decrease of size of the floating gate, in particular, reduces capacitive coupling to the floating gate normally employed for programming of the memory and thus reduces writing speed. Increase of word line and bit line resistivity also reduces writing speed and prior art designs have been constrained to the use of doped semiconductor material which has a significant specific resistance for interconnection of circuits contained in the memory.
Additionally, standard designs for EEPROMs of the double poly type which employ a first layer of polysilicon as the floating gate and a second layer of polysilicon as the control or select gate presents a topography problem which compromises quality of an oxide insulating layer used to separate them. Severe topology also restricts the use of metals in connections to elements of the memory since deposition of metals over severe topology is not fully reliable and may cause opens due to metal migration. Thus use of polysilicon for conductors rather than metal tends to increase resistivity. Further, when recessed oxide (ROX) isolation is used, the non-planar surface presents a problem with exposure resolution during lithographic patterning due to limitations on the defocus window (e.g. depth of field). This limitation is especially severe in high numerical aperture tools used for high speed exposure. These limitations can easily cause a reduction of throughput and/or a reduction of manufacturing yield; either of which tends to increase costs of EEPROMs.
Unfortunately, the severe topology actually has advantages in the operation of EEPROMS since it increases the so-called capacitance ratio: the ratio of the control gate capacitance to the capacitance of the floating gate or, more specifically, the ratio of the area of the control gate oxide to the area of the tunnelling oxide since the floating gate between the control gate and the substrate or well forms a capacitive voltage divider. This ratio must generally be kept above a particular value related to the programming voltage for operability and operational reliability increases with increase of this ratio at a given programming voltage. Since the tunnelling oxide is generally planar, the severe topology of the control gate oxide and the control gate, itself, increases the capacitance of the control gate and the capacitance ratio. Accordingly, severe topology has been conventionally tolerated in view of the increase in operational reliability it provides even though manufacturing yield is somewhat compromised.